London – October 19, 2026 -- The global 3D through-silicon-via (TSV) and 2.5D packaging market will grow from USD 9.46 billion in 2025 to USD 21.50 billion by 2035, according to Credence Research. That implies a compound annual growth rate of 8.50% for 2026-2035. The figures are the firm's proprietary model estimates, not audited supplier sales totals.
HBM and data centers account for the largest share of spending
High-bandwidth memory (HBM) and other memory made up 46.0% of 2025 application revenue. Data centers and high-performance computing held 55.0% of end-use spending. By technology, 2.5D integration led with 38.0% of 2025 value, and die-to-wafer integration accounted for 48.0%.
The market is narrower than advanced packaging as a whole. It covers via formation, silicon interposers and stacking services, and excludes the value of semiconductor dies, fabrication equipment, bridge-only packages without TSVs and fan-out packages without vias.
North America leads at 35.0% while Middle East and Africa grows fastest at 9.96%
North America held 35.0% of 2025 value, driven by U.S. AI accelerator designers and cloud buyers, even where assembly takes place in Asia. Asia Pacific followed at 33.0%, with Taiwan, South Korea and Japan hosting major HBM producers, foundries and outsourced packaging capacity. Europe accounted for 22.0%, Middle East and Africa for 6.0% and Latin America for 4.0%.
Middle East and Africa has the fastest modeled growth, at 9.96% annually from a small base. Demand there is supported by AI data center investment and runs mainly through imported accelerators.
AI accelerator design multiplies vias per package
AI accelerators pair multiple HBM stacks with processor dies, which raises demand for vias and larger interposers per package. Chiplet architectures add further need for precise alignment, bonding and testing. Packaging investment in the United States and Asia is expanding capacity, but new plants face long qualification periods and possible construction delays.
Yield risk and alternative designs cap the upside
TSV fabrication involves etching, insulation, metal filling, wafer thinning and bonding. Each step carries yield risk, and one failed die can reduce the value of a complex multi-die package. Taller stacks make heat removal and mechanical stress harder to manage. Bridge and organic-interposer approaches can displace TSV-intensive designs where full silicon interposers cost too much.
Credence names concentration among a small group of AI buyers, plant timing and the cost of new bonding and thermal processes as the principal risks. Mature image-sensor and MEMS applications provide a steadier but slower-growing base.
TSMC and Amkor sign 10-year Arizona packaging deal; Samsung ships HBM4
SK hynix, Samsung Electronics and Micron lead HBM stacking. TSMC provides silicon-interposer integration, while ASE Technology Holding and Amkor Technology handle advanced assembly and test. Credence says competition centers on stacking yield, capacity, thermal performance and customer qualification rather than published stand-alone TSV revenue.
On June 16, 2026, TSMC and Amkor announced a 10-year agreement for advanced packaging and testing services in Arizona. It sets a framework for U.S. capacity, and financial terms were not disclosed. On Feb. 12, 2026, Samsung said it had begun mass production and commercial shipments of HBM4.