Santa Clara – September 20, 2026 -- Dnotitia Inc. has received back the first ASIC samples of its Vector Data Processing Unit (VDPU) from fabrication, with chip-level characterization now underway and silicon-based server evaluations scheduled for the fourth quarter of 2026. The company disclosed the milestone at AI Infra Summit 2026, held Sept. 15-17 at the Santa Clara Convention Center, where it showcased a server-scale VDPU architecture built for vector retrieval workloads in retrieval-augmented generation and agentic AI systems.
FPGA tests show a four-card VDPU server outperforming dual-socket CPU servers by 5.77x
On Dnotitia's FPGA evaluation platform, a server fitted with four VDPU cards delivered up to 5.77 times the vector-search throughput of an identical software stack running on a dual-socket CPU-only server, while matching or exceeding recall accuracy. In a 4,096-dimensional multimodal workload, the VDPU cut host CPU usage during index building by 92% and host memory consumption by 73%, freeing CPU capacity for application-layer processing. Dnotitia noted that all figures were captured on the FPGA platform and do not represent final ASIC performance.
Dnotitia targets up to 10x throughput once the ASIC-based server ships
The company is targeting up to 10x vector-search performance versus a CPU-based server once its VDPU ASIC-based server platform is operational. The FPGA platform has already been validated against FAISS, Milvus and hnswlib across brute-force KNN, IVF, NSW and HNSW indexing methods, and Dnotitia plans to extend ASIC support to a broader set of vector libraries and databases to match customer environments already in production.
Chief Technology Officer Se-Hyun Yang frames retrieval as the new infrastructure bottleneck
"Agentic AI is shifting the AI infrastructure bottleneck from model compute toward retrieval,