Austin, Texas – – September 13, 2026 -- La Luce Cristallina has launched a 0.5-micrometer silicon-based quantum paraelectric strontium titanate on insulator (QP-STOI) wafer platform, giving researchers and national laboratories a new tool for building next-generation cryogenic and quantum devices.
New STO layer is 100 times thicker than conventional buffer layers used in epitaxial growth on silicon
Built on a thick layer of silicon dioxide, the bulk-like, highly insulating STO layer enables organizations to exploit strontium titanate's voltage-tunable dielectric behavior at cryogenic temperatures. At these temperatures, STO enters a quantum paraelectric state where dielectric properties respond strongly to applied electric fields, supporting parametric amplifiers for qubit readout, tunable microwave components and future electro-optic devices. The platform also exhibits tunable piezoelectric properties for research into electrically controlled actuators and precision sensors.
Platform ships in 2-inch wafers today, with 200-millimeter scale-up planned for early next year
The wafers are CMOS- and foundry-compatible, allowing direct integration into existing semiconductor manufacturing lines. La Luce Cristallina currently supplies the platform in 2-inch format, with plans to scale to 200 millimeters in early 2027.
U.S. government has committed more than $2 billion across nine quantum companies to expand domestic manufacturing
The launch follows a U.S. Department of Commerce announcement of over $2 billion in planned investments across nine quantum firms to accelerate domestic quantum manufacturing. NIST has also opened a Quantum Manufacturing Engineering Center to advance scalable quantum component production.
Alex Demkov, CEO of La Luce Cristallina, said the wafer combines quantum paraelectric behavior with foundry-compatible manufacturing to help researchers explore new architectures for quantum sensing and qubit readout.