Hsinchu – September 24, 2026 -- M31 Technology and Ambiq have jointly developed a Foundation IP solution on TSMC's N12e process that cuts leakage power by approximately 50% for always-on edge AI and AIoT chips, the companies announced at the TSMC 2026 North America Open Innovation Platform Ecosystem Forum.
Joint IP stack targets tightening power and area budgets for wearables and AIoT
The solution pairs an optimized SPSRAM memory compiler with an ultra-low-leakage standard-cell library built specifically for Ambiq's chip platforms. As SoC designs add more embedded intelligence, power targets have tightened while die-size limits and tape-out schedules remain fixed, pushing designers toward foundation-level efficiency gains rather than late-stage fixes.
Memory compiler hits near-500 MHz while capping retention leakage at 1.05-1.1x
The TSMC N12e ULL SPSRAM compiler supports both high-performance and ultra-low-power modes within the same physical memory footprint. Its dual-rail architecture reaches close to 500 MHz at near-threshold periphery voltage in low-power mode, while VCCA retention leakage stays within 1.05-1.1x of total bit-cell retention leakage. The compiler also integrates redundancy, power gating, and BIST features, with full development still ongoing after initial instances showed strong PPA gains.
Standard-cell library delivers roughly 50% leakage power savings for Ambiq platforms
M31's complementary N12e standard-cell library was co-developed with Ambiq, combining Ambiq's cascade-style circuit approach with M31's layout innovations to cut leakage power by approximately 50%. The companies say the combined IP stack shortens design cycles, reduces die size, and lowers redesign effort for customers targeting aggressive power, performance, and area (PPA) goals.
Executives frame the collaboration as foundational to next-generation edge AI platforms
Scott Hanson, CTO and Founder of Ambiq, said the collaboration contributed key building blocks to the company's next-generation flagship platform on the N12e node. Jayanta Lahiri, VP at M31, said the combined memory compiler and standard-cell foundations give customers a practical, implementation-ready path to meet unprecedented energy and area targets.
M31 said it will continue expanding its low-power IP portfolio on advanced process nodes with ecosystem partners to support future edge AI applications.