IBM and Siemens Team Up to Move 3D Nanostack Chips Toward Production
Albany – October 14, 2026 -- IBM and Siemens have launched a joint research program to prepare IBM's nanostack transistor architecture, which packs nearly 100 billion transistors into a space the size of a fingernail at the 7 angstrom node, for volume manufacturing.
Nanostack stacks and staggers transistors in three dimensions
IBM describes nanostack as the industry's first known three-dimensional, nanosheet-based design. It vertically stacks and staggers transistors to raise density. The architecture also allows different material combinations in each stacked layer, so each transistor's performance and power efficiency can be optimized independently of the other.
IBM credits the design with substantial gains in energy efficiency, performance and SRAM scaling. It unveiled the architecture earlier this year and has demonstrated that it is viable.