Albany – October 14, 2026 -- IBM and Siemens have launched a joint research program to prepare IBM's nanostack transistor architecture, which packs nearly 100 billion transistors into a space the size of a fingernail at the 7 angstrom node, for volume manufacturing.
Nanostack stacks and staggers transistors in three dimensions
IBM describes nanostack as the industry's first known three-dimensional, nanosheet-based design. It vertically stacks and staggers transistors to raise density. The architecture also allows different material combinations in each stacked layer, so each transistor's performance and power efficiency can be optimized independently of the other.
IBM credits the design with substantial gains in energy efficiency, performance and SRAM scaling. It unveiled the architecture earlier this year and has demonstrated that it is viable.
Siemens contributes EDA, simulation and lithography expertise to close the production gap
IBM says further advances are needed before nanostack is ready for manufacturing and production at scale. Siemens brings electronic design automation (EDA), process simulation, lithography optimization and advanced manufacturing software to the work.
The partners will advance the design, simulation and lithography techniques needed for nanostack and for future generations beyond the current 7 angstrom node. A core deliverable is a set of advanced virtual models of nanostack. These will be used to model performance, optimize designs and address fabrication challenges before chips are built.
Both companies tie the effort to AI-driven logic scaling demand
Huiming Bu, IBM's Vice President of Silicon Technology R&D, said nanostack is meant to shift device scaling from 2D to 3D. He described it as a path for the logic scaling needed to support AI and other emerging technologies over the coming decade.
Ankur Gupta, Siemens' Executive Vice President for EDA IC Portfolio, said angstrom-era scaling requires tightly coupled co-optimization between device physics, EDA design and manufacturing software, and manufacturing. He said physical AI places extraordinary demands on silicon architecture. Siemens aims to address physical limitations early through virtual modeling, simulation, lithography and design software optimizations.
The companies aim to shorten technology development cycles and build the manufacturing foundation needed to bring nanostack toward production. The source gives no timeline, financial terms or production targets for the collaboration.