San Jose, Calif. – September 22, 2026 -- GS Microelectronics U.S. (GSME) and Teradyne, Inc. (NASDAQ: TER) have signed a multi-year strategic partnership to build a semiconductor test and evaluation center at GSME's new 42,000-square-foot Silicon Valley headquarters, with the facility set to open in Q4 2026.
GSME will run a dedicated Teradyne-equipped test floor for next-generation chips
The center will deploy Teradyne's latest test handlers, probers, and automated test systems to support customer demonstrations, device evaluations, engineering development, pilot production, and technical training. Target applications include AI hyperscaler devices, silicon photonics, automotive semiconductors, power management, and RF technologies.
GSME expands engineering headcount across four regions
GSME is growing its test engineering team in the United States, Taiwan, Europe, and the Gulf Cooperation Council region to handle design-in engagements, test program development, and customer-specific application work tied to the new center.
Executives cite AI-driven complexity as the deal's commercial driver
"Standardizing on Teradyne's flagship test platforms enhances our custom silicon and manufacturing enablement services while giving customers a seamless pathway from device evaluation and test development to production readiness," said Farhat Jahangir, President and CEO of GSME. Shannon Poulin, President of Teradyne's Semiconductor Test Group, said the partnership pairs Teradyne's test platforms with GSME's engineering expertise to move customers from development into volume production as AI data center buildouts increase design complexity.
Joint sales push targets faster Teradyne-based design wins
The companies will run joint sales engagements, target account development, technical workshops, and customer briefings aimed at broadening adoption of Teradyne-based test solutions. Customer demonstrations and evaluations at the new center are expected to begin shortly after the Q4 2026 opening.